1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a plurality of bus lines providing coupling between a circuit unit and input/output circuits.
2. Description of Related Art
In a semiconductor integrated circuit, in order to improve the data processing capacity of a memory, bus lines tend to be broadened, because a sufficient improvement is not achieved only by increasing the operating frequency of the memory core. Especially, a memory macro incorporated in a logic chip is advantageous for realizing high performance and low power in terms of the fact that bus lines can be broadened, because such memory macro is not influenced by an interface (I/F) between product chips. On the other hand, memory capacity is growing more and more and a memory macro having a larger area adopts a manner in which a memory cell array plate is divided into a plurality of banks, one of which can be selected. The adoption of this manner is effective for reducing the power consumed by the memory cell array plate and achieving a higher rate. However, if data width (the number of bits) is large, an increasing number of bus lines will be required to intercouple the banks. There is a problem of an enlargement of a macro area due to limitation of wiring resources in an upper layer, not circuit elements. This problem is improved by increasing the number of wiring layers over the macro, which, however, anyway, results in a problem of cost increase. Some situations are encountered where current consumed by a bus wiring section exceeds that consumed by the memory plate. This poses another problem of growing of power consumption by bus wiring. The problem of growing of power consumption by bus wiring is currently addressed by design efforts in which as many bus lines as possible are laid with a minimum wiring pitch. If data width (the number of bits) and memory capacity further increase along these trends, it is predicted in future that the tradeoff problem between growing of power consumption due to an increase in wiring capacity and cost increase becomes more severe.
From the foregoing viewpoint, Japanese Unexamined Patent Publication No. Hei8 (1996)-96571 discloses a configuration in which memory blocks are divided into two banks (regions) and data lines (bus lines) which are used to switch between the two banks are laid in a vertical direction with respect to a row of input/output pads (I/O pads) and wired to extend over the memory blocks within the banks.
Japanese Unexamined Patent Publication No. Hei8 (1996)-96571 also discloses a configuration in which two banks are disposed in parallel with a row of I/O pads as an example of related art (see FIG. 7; a first example of related art). Here, bus lines are laid separately between each bank and each I/O pad and switching between the banks is performed by a multiplexer circuit (MPX circuit) attached to each I/O pad. In a case where the I/O pads are arranged alongside the entire horizontal dimension of the two banks, a bus wiring region (resources) large enough to wire the number of data buses to extend laterally along the horizontal sides of the two banks is required (bus wiring is depicted in FIG. 7 with the assumption that data width (the number of bits)=4 for simplicity).
In addition, a data bus wiring configuration which is regarded as the most general one is shown in FIG. 8 as a second example of related art. Here, this wiring configuration includes common bus lines BUS11, BUS22, BUS33, BUS44 wired between two banks and shared for each data bit. Each of DQ1 to DQ4 is provided therein with a tristate buffer which switches over between enabling and disabling data transfer from/to it through the bus line terminated in it according to a bank selection.